In 2017, IEEE Design&Test published a special issue on “3D-TEST” (referring to both the workshop with that name, as well as the topic), featuring three articles on various test-related issues of the AMD Radeon R9 Fury, a marvel of multidimensional packaging. Since then, the market has lurched tentatively in the same direction. Expectations were high for single-tower many-die stacks, but the realities of power and thermal issues still hold that promise at bay. Slowly, the market has been tackling each obstacle placed in front of it. Once thought to be a mere stepping-stone to true 3D-IC stacking, side-by-side stacking onto an interposer has created its own place on the product roadmaps and is here to stay. The word “chiplet” has yet to claim space in the dictionary, but chiplets (dies meant to be stacked as part of a larger chip) are front and center in advanced chip design projects. Placed upon passive or active interposers, these building blocks enable the path to heterogeneous integration: architecting submodules of a package with various technology nodes, and therefore with just the right balance of performance and cost. The debate has shifted to interchiplet communications. HBI+ and OpenHBI, ultra-short reach(USR)/extra-short reach (XSR), and the nascent Universal Chiplet Interconnect Express (UCIe) interface are battling for the structured high-speed interconnect market. Certainly, memory stacking has won with high bandwidth memory (HBM) stacks seen on several production devices.

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客座编辑介绍：多芯片封装设计与测试特刊

2017年，IEEE设计与测试发表了一篇关于“3D-TEST”的特刊（既指具有该名称的研讨会，也指该主题），其中包括三篇关于多维封装奇迹 AMD Radeon R9 Fury 的各种测试相关问题的文章。从那以后，市场试探性地朝同一方向倾斜。对单塔多芯片堆栈的期望很高，但功率和热问题的现实仍然阻碍了这一承诺。慢慢地，市场一直在解决摆在它面前的每一个障碍。曾经被认为是真正的 3D-IC 堆叠的垫脚石，并排堆叠到中介层上已在产品路线图上创造了自己的位置，并将继续存在。“chiplet”这个词还没有在字典中占据一席之地，但小芯片（意在作为更大芯片的一部分堆叠的芯片）是先进芯片设计项目的前沿和中心。这些构建块放置在无源或有源中介层上，可以实现异构集成：使用各种技术节点构建封装的子模块，因此在性能和成本之间取得了恰到好处的平衡。争论已经转移到小芯片间通信上。HBI+ 和 OpenHBI、超短距离 (USR)/超短距离 (XSR) 以及新生的通用 Chiplet Interconnect Express (UCIe) 接口正在争夺结构化高速互连市场。当然，内存堆叠已经赢得了在多个生产设备上看到的高带宽内存 (HBM) 堆栈。使用各种技术节点构建包的子模块，因此在性能和成本之间取得了恰到好处的平衡。争论已经转移到小芯片间通信上。HBI+ 和 OpenHBI、超短距离 (USR)/超短距离 (XSR) 以及新生的通用 Chiplet Interconnect Express (UCIe) 接口正在争夺结构化高速互连市场。当然，内存堆叠已经赢得了在多个生产设备上看到的高带宽内存 (HBM) 堆栈。使用各种技术节点构建包的子模块，因此在性能和成本之间取得了恰到好处的平衡。争论已经转移到小芯片间通信上。HBI+ 和 OpenHBI、超短距离 (USR)/超短距离 (XSR) 以及新生的通用 Chiplet Interconnect Express (UCIe) 接口正在争夺结构化高速互连市场。当然，内存堆叠已经赢得了在多个生产设备上看到的高带宽内存 (HBM) 堆栈。新兴的通用小芯片互连高速 (UCIe) 接口正在争夺结构化高速互连市场。当然，内存堆叠已经赢得了在多个生产设备上看到的高带宽内存 (HBM) 堆栈。新兴的通用小芯片互连高速 (UCIe) 接口正在争夺结构化高速互连市场。当然，内存堆叠已经赢得了在多个生产设备上看到的高带宽内存 (HBM) 堆栈。