Editor’s notes: The ”chiplet” components that, after stacking, constitute a multidie package, can be complex system-on-chips in their own right. Consequently, IEEE Std 1838, the recently released standard for test access in 3-D die stacks, potentially interacts with many other Design-for- Test (DfT) standards, which all might have been used in these chiplets. This article provides a guided tour through the growing set of IEEE DfT standards in the context of an IEEE 1838-compliant design. —Erik Jan Marinissen, imec

中文翻译：

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将 IEEE 测试标准应用于多芯片设计


编者注：“小芯片”组件在堆叠后构成多芯片封装，其本身可以是复杂的片上系统。因此，最近发布的 3D 芯片堆栈测试访问标准 IEEE Std 1838 可能与许多其他测试设计 (DfT) 标准交互，而这些标准都可能已在这些小芯片中使用。本文提供了在 IEEE 1838 兼容设计背景下不断增长的 IEEE DfT 标准的导览。 —Erik Jan Marinissen，imec