In this work, we successfully fabricated vertical homo-junction In_0.53Ga_0.47As tunneling field-effect transistors (TFETs) by a top-down approach. We particularly focused on recovery of the sidewall damage induced during dry etching of the In_0.53Ga_0.47As layer. The recovery steps comprised a series of digital etching cycles, short wet etching of the In_0.53Ga_0.47As layer, and (NH₄)₂S-based treatment. The fabricated device with a gate length of 100 nm exhibited a minimum subthreshold swing of 52 mV/decade at room temperature and an average subthreshold swing of 60 mV/decade over more than two decades of drain current. We also fabricated and analyzed In_0.53Ga_0.47As metal-oxidesemiconductor capacitors and metal-oxidesemiconductor field-effect transistors to investigate the effect of the S-treatment on their electrical characteristics.

在这项工作中，我们通过自上而下的方法成功地制造了垂直同质结 In _0.53 Ga _{0.47 As 隧穿场效应晶体管 (TFET)。我们特别关注在 In 0.53} Ga _0.47 As 层的干法蚀刻过程中引起的侧壁损伤的恢复。恢复步骤包括一系列数字蚀刻循环、In _0.53 Ga _0.47 As 层的短湿蚀刻和 (NH ₄ ) ₂S型治疗。栅极长度为 100 nm 的制造器件在室温下表现出 52 mV/decade 的最小亚阈值摆幅，在超过 20 个漏极电流的情况下，平均亚阈值摆幅为 60 mV/decade。我们还制作并分析了 In _0.53 Ga _0.47 As 金属氧化物半导体电容器和金属氧化物半导体场效应晶体管，以研究 S 处理对其电特性的影响。