In this letter, the field-programmable gate array (FPGA) accelerated implementation of matrix-assembly phase of the method of moments (MoM) is presented. The solution is based on a discretization of the frequency-domain mixed potential integral equation using the Rao–Wilton–Glisson basis functions and their extension to wire-to-surface junctions. To take advantage of the given hardware resources (i.e., Xilinx Alveo U200 accelerator card), nine independent processing paths/runtime efficient compute units are developed and synthesized. Numerical results provided for a quadrifilar spiral antenna mounted on a conductive handset box show that the proposed parallelization scheme performs 9.53× faster than a traditional (i.e., serial) central processing unit (CPU) MoM implementation, and about 1.67× faster than a parallel six-core CPU MoM implementation.

中文翻译：

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基于 RWG 的 MoM 矩阵组装阶段的 FPGA 加速

在这封信中，介绍了矩量法 (MoM) 的矩阵组装阶段的现场可编程门阵列 (FPGA) 加速实现。该解决方案基于使用 Rao-Wilton-Glisson 基函数的频域混合势积分方程的离散化及其对线对面结的扩展。为了利用给定的硬件资源（即 Xilinx Alveo U200 加速器卡），开发和综合了九个独立的处理路径/运行时高效计算单元。为安装在导电手机盒上的四线螺旋天线提供的数值结果表明，所提出的并行化方案的执行速度比传统（即串行）中央处理器 (CPU) MoM 实现快 9.53 倍，比并行六-core CPU MoM 实现。