The versatile video coding standard H.266/VVC release has been accompanied with various new contributions to improve the coding efficiency beyond the high-efficiency video coding (HEVC), particularly in the transformation process. The adaptive multiple transform (AMT) is one of the new tools that was introduced in the transform module. It involves five transform types from the discrete cosine transform/discrete sine transform families with larger block sizes. The DCT-II has a fast computing algorithm, while the DST-VII relies on a complex matrix multiplication. This has led to an additional computational complexity. The approximation of the DST-VII can be used for the transform optimization. At the hardware level, this method can provide a gain in power consumption, logic resources use and speed. In this paper, a unifed two-dimensional transform architecture that enables exact and approximate DST-VII computation of sizes \(8\times 8, 8\times 16, 8\times 32, 16\times 8, 16\times 16, 16\times 32, 32\times 8, 32\times 16\) and \(32\times 32\) is proposed. The exact transform computation can be processed using either multipliers or the MCM algorithm, while the approximate transform computation is based on additions and bit-shifting operations. All the designs are implemented under the Arria 10 FPGA device. The synthesis results show that the proposed design implementing the approximate transform matrices is the most efficient method with only 4% of area consumption. It reduces the logic utilization by more than 65% compared to the multipliers-based exact transform design, while about 53% of hardware cost saving is obtained when compared to the MCM-based computation. Furthermore, the approximate-based 2D transform architecture can operate at 78 MHz allowing a real-time coding for 2K and 4K videos at 100 and 25 frames/s, respectively.

多功能视频编码标准 H.266/VVC 的发布伴随着各种新的贡献，以提高超越高效视频编码 (HEVC) 的编码效率，特别是在转换过程中。自适应多重变换 (AMT) 是变换模块中引入的新工具之一。它涉及来自具有较大块大小的离散余弦变换/离散正弦变换系列的五种变换类型。DCT-II 具有快速计算算法，而 DST-VII 依赖于复矩阵乘法。这导致了额外的计算复杂性。DST-VII 的近似值可用于变换优化。在硬件层面，这种方法可以提高功耗、逻辑资源使用和速度。在本文中，\(8\times 8, 8\times 16, 8\times 32, 16\times 8, 16\times 16, 16\times 32, 32\times 8, 32\times 16\)和\(32\times 32 \)被提议。可以使用乘法器或 MCM 算法来处理精确的变换计算，而近似变换计算基于加法和位移操作。所有设计均在 Arria 10 FPGA 器件下实现。综合结果表明，所提出的实现近似变换矩阵的设计是最有效的方法，仅占用 4% 的面积。与基于乘法器的精确变换设计相比，它的逻辑利用率降低了 65% 以上，而与基于 MCM 的计算相比，硬件成本节省了约 53%。此外，基于近似的 2D 变换架构可以在 78 MHz 下运行，允许分别以 100 和 25 帧/秒的速度对 2K 和 4K 视频进行实时编码。