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A 40-nm low-power WiFi SoC with clock gating and power management strategy
International Journal of Electronics ( IF 1.1 ) Pub Date : 2022-09-09 , DOI: 10.1080/00207217.2022.2118843
Han Su 1 , Jianbin Liu 2 , Yanfeng Jiang 1
Affiliation  

ABSTRACT

With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7.



中文翻译:

具有时钟门控和电源管理策略的 40 nm 低功耗 WiFi SoC

摘要

随着物联网(IoT)行业的兴起,智能电源插头、安全ID标签、家庭自动化和可穿戴电子设备等应用都使得低功耗WiFi芯片的需求迫切。本文采用40 nm CMOS工艺设计并实现了低功耗2.4 GHz 802.11b/g/n WiFi片上系统(SoC),面积为8.1 mm 2。该低功耗SoC集成了32位微控制器、802.11b/g/n WiFi基带、2.4GHz射频收发器、充足的存储空间、ADC、6通道PWM、灵活的I/O接口、多级电源管理模块等具有多种睡眠模式,漏电流极低,浅/深睡眠模式下漏电流为 0.8 mA/12 µA,关断模式下漏电流为 0.4 µA,以降低功耗。展示了高性能,包括 20.1 dBm/19.1 dBm 的 Pout (−28 dB/-30 dB EVM) 和 −76 dBm/-74 dBm 的 RX 灵敏度,同时 54 Mbps 的总电流为 148.5 mA/146.5 mA (TX) OFDM/HT20 MCS7。

更新日期:2022-09-09
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