The crucial role played by digital multipliers in VLSI system design makes it indispensable to study the PPA cards of digital multiplier architectures before tailoring multiplier architecture into such systems. Therefore, in this work, we present a detailed investigation and analysis of PPA cards of popular digital multiplier architectures, for various wordlengths. Each multiplier has been implemented on Artix-7 FPGA xc7a200tfbg676-2 and analyzed using Xilinx Vivado Design Suite 2019.2. A major contribution in this paper is the study of energy profiles of the architectures, not focused on in the earlier literature. This study compares their device utilization, timing parameters, power consumption, and energy profiles. Results indicate that Dadda Tree Multiplier and Wallace Tree Multiplier (460 slices and 557 slices, respectively, for $N=32$ bits) are undoubtedly the least slices consuming fast multipliers, but their power consumption and energy density are high as well. For 32-bit implementation, Vedic Multiplier consumes 48.9% lower power than Dadda Tree Multiplier, while the latter occupies 30.42% lesser slices. The speed of the Vedic Multiplier is in close proximity with the tree multipliers. The energy density of Vedic Multiplier (0.3$$nJ/slice) is much lower than that of Dadda Tree Multiplier (0.77$$nJ/slice).

数字乘法器在 VLSI 系统设计中所起的关键作用使得在将乘法器架构定制到此类系统之前，研究数字乘法器架构的 PPA 卡是必不可少的。因此，在这项工作中，我们针对各种字长对流行的数字乘法器架构的 PPA 卡进行了详细调查和分析。每个乘法器已在 Artix-7 FPGA xc7a200tfbg676-2上实现并使用 Xilinx Vivado Design Suite 2019.2 进行分析。本文的一个主要贡献是对架构能量分布的研究，而不是早期文献中的重点。本研究比较了它们的设备利用率、时序参数、功耗和能量配置文件。结果表明，达达树乘法器和华莱士树乘法器（分别为 460 片和 557 片，用于$ñ=32$位）无疑是消耗快速乘法器最少的切片，但它们的功耗和能量密度也很高。对于 32 位实现，Vedic Multiplier 的功耗比 Dadda Tree Multiplier 低 48.9%，而后者占用的片少 30.42%。吠陀乘法器的速度与树乘法器非常接近。吠陀乘数的能量密度（0.3$$nJ/slice）远低于达达树乘数（0.77$$nJ/片）。