The traditional sub-sampling phase-locked loop faces the tradeoffs between phase noise and spur, in that low in-band phase noise requires large sampling capacitor size but at the sacrifice of spur performance. This paper presents a sub-sampling PLL aimed at minimizing in-band phase noise via sampling thermal noise cancellation technique. It enables the substantial reduction of in-band phase noise while reducing the sampling capacitor size. In addition, due to the reduction of the sampling capacitance, the reference spur performance of the PLL is improved, and the power consumption of the isolation buffer is reduced. Implemented in a 65 nm CMOS process, the in-band phase noise at 200 kHz offset is −133.4 dBc/Hz at 2.2 GHz and integrated jitter is 80 fs_rms. The reference spur is −67 dBc. It consumes 5.5 mA from 1.2 V supply and occupies 0.72 mm².

中文翻译：

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一种具有采样热噪声消除技术的低抖动子采样锁相环

传统的子采样锁相环面临着相位噪声和杂散之间的权衡，因为低带内相位噪声需要大采样电容尺寸，但牺牲了杂散性能。本文介绍了一种子采样 PLL，旨在通过采样热噪声消除技术最大限度地减少带内相位噪声。它可以显着降低带内相位噪声，同时减小采样电容器的尺寸。此外，由于采样电容的减小，PLL的参考杂散性能得到改善，隔离缓冲器的功耗降低。采用 65 nm CMOS 工艺实现，200 kHz 偏置时的带内相位噪声在 2.2 GHz 时为 −133.4 dBc/Hz，集成抖动为 80 fs _rms. 参考杂散为 −67 dBc。它从 1.2 V 电源消耗 5.5 mA 电流，占用 0.72 mm ²。