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CNT-molecule-CNT (1D-0D-1D) van der Waals integration ferroelectric memory with 1-nm2 junction area
Nature Communications ( IF 14.7 ) Pub Date : 2022-08-12 , DOI: 10.1038/s41467-022-32173-8
Thanh Luan Phan 1 , Sohyeon Seo 2 , Yunhee Cho 2, 3 , Quoc An Vu 3, 4 , Young Hee Lee 3, 4 , Dinh Loc Duong 3, 4 , Hyoyoung Lee 2, 3 , Woo Jong Yu 1
Affiliation  

The device’s integration of molecular electronics is limited regarding the large-scale fabrication of gap electrodes on a molecular scale. The van der Waals integration (vdWI) of a vertically aligned molecular layer (0D) with 2D or 3D electrodes indicates the possibility of device’s integration; however, the active junction area of 0D-2D and 0D-3D vdWIs remains at a microscale size. Here, we introduce the robust fabrication of a vertical 1D-0D-1D vdWI device with the ultra-small junction area of 1 nm2 achieved by cross-stacking top carbon nanotubes (CNTs) on molecularly assembled bottom CNTs. 1D-0D-1D vdWI memories are demonstrated through ferroelectric switching of azobenzene molecules owing to the cis-trans transformation combined with the permanent dipole moment of the end-tail -CF3 group. In this work, our 1D-0D-1D vdWI memory exhibits a retention performance above 2000 s, over 300 cycles with an on/off ratio of approximately 105 and record current density (3.4 × 108 A/cm2), which is 100 times higher than previous study through the smallest junction area achieved in a vdWI. The simple stacking of aligned CNTs (4 × 4) allows integration of memory arrays (16 junctions) with high device operational yield (100%), offering integration guidelines for future molecular electronics.



中文翻译:

CNT-分子-CNT (1D-0D-1D) 范德瓦尔斯集成铁电存储器,结面积为 1-nm2

该设备的分子电子学集成在分子尺度上大规模制造间隙电极方面受到限制。垂直排列的分子层 (0D) 与 2D 或 3D 电极的范德华集成 (vdWI) 表明器件集成的可能性;然而,0D-2D 和 0D-3D vdWI 的有源结区仍保持在微型尺寸。在这里,我们介绍了垂直 1D-0D-1D vdWI 器件的稳健制造,该器件具有 1 nm 2的超小结面积,这是通过在分子组装的底部 CNT 上交叉堆叠顶部碳纳米管 (CNT) 实现的。1D-0D-1D vdWI 记忆通过偶氮苯分子的铁电转换来证明,这是由于顺反转换与末端-CF 3的永久偶极矩相结合团体。在这项工作中,我们的 1D-0D-1D vdWI 存储器表现出超过 2000 秒的保持性能,超过 300 个循环,开/关比约为 10 5和记录电流密度 (3.4 × 10 8  A/cm 2 ),这是通过 vdWI 中实现的最小结面积,比之前的研究高 100 倍。排列整齐的碳纳米管 (4 × 4) 的简单堆叠允许以高器件运行产量 (100%) 集成存储器阵列(16 个结),为未来的分子电子学提供集成指南。

更新日期:2022-08-12
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