Reliability aspects such as bias temperature instability (BTI) and hot carrier injection (HCI) affecting devices in advanced CMOS-based technology have been the subject of active research in recent decades. Due to these reliability issues, various digital and analog circuits were investigated for degradation. However, circuit blocks like the neuron circuits of neuromorphic systems are not fully explored. This work is inclined toward examining the collective degradation impact of BTI and HCI due to aging in an adaptive exponential “integrate and fire” (I&F) model-based, neuromorphic neuron circuit. Detailed degradation analysis of the stimulated neuron circuit aided in identifying possible mismatches/faults associated with neuron spikes. These factors could reduce the efficiency of the neuronal circuit by potentially affecting the transmission of information in a neuromorphic system. Various performance parameters were then derived to quantify the extent of circuit deterioration. The proposed reliability-aware design aims to improve the circuit degradation through its effectiveness in alleviating the overall reliability impact. It demonstrates enhanced circuit operation in spike generation even after aging. The circuit performance is validated through simulations at “Time0” (pre-degradation) and “Aged” (post-degradation) neuron netlists, which is then compared with the proposed reliability-aware circuit.

中文翻译：

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使用神经形态电路的可靠性感知设计实现高效速率和时间编码

近几十年来，影响基于先进 CMOS 技术的器件的可靠性方面，例如偏置温度不稳定性 (BTI) 和热载流子注入 (HCI)，一直是积极研究的主题。由于这些可靠性问题，研究了各种数字和模拟电路的退化情况。然而，像神经形态系统的神经元电路这样的电路块还没有得到充分探索。这项工作旨在检查 BTI 和 HCI 的集体退化影响，原因是在基于自适应指数“集成和激发”(I&F) 模型的神经形态神经元电路中老化。受激神经元电路的详细退化分析有助于识别与神经元尖峰相关的可能失配/故障。这些因素可能会影响神经形态系统中的信息传输，从而降低神经回路的效率。然后推导出各种性能参数来量化电路退化的程度。所提出的可靠性感知设计旨在通过其在减轻整体可靠性影响方面的有效性来改善电路退化。它展示了即使在老化后尖峰生成中增强的电路操作。通过在“Time0”（退化前）和“老化”（退化后）神经元网表进行仿真来验证电路性能，然后将其与建议的可靠性感知电路​​进行比较。所提出的可靠性感知设计旨在通过其在减轻整体可靠性影响方面的有效性来改善电路退化。它展示了即使在老化后尖峰生成中增强的电路操作。通过在“Time0”（退化前）和“老化”（退化后）神经元网表进行仿真来验证电路性能，然后将其与建议的可靠性感知电路​​进行比较。所提出的可靠性感知设计旨在通过其在减轻整体可靠性影响方面的有效性来改善电路退化。它展示了即使在老化后尖峰生成中增强的电路操作。通过在“Time0”（退化前）和“老化”（退化后）神经元网表进行仿真来验证电路性能，然后将其与建议的可靠性感知电路​​进行比较。