A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects,International Journal of Circuit Theory and Applications

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A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects
International Journal of Circuit Theory and Applications ( IF 1.8 ) Pub Date : 2022-07-27 , DOI: 10.1002/cta.3392
Prema Kumar Govindaswamy ₁ , Vijaya Sankara Rao Pasupureddi ₂

Affiliation

This work proposes a power-efficient half-rate current-integrating logic (CIL) echo cancelation hybrid circuit topology for full-duplex communication for off-chip interconnects in 65 nm CMOS. The proposed hybrid topology has a low power consumption compared to traditional current-mode hybrid circuit topology implementations, thanks to the CIL hybrid topology with sample and hold front-end. The post-layout performance of the half-rate CIL hybrid includes package parasitic has a differential received signal voltage swing of 190 mV at 10 Gb/s data rate with a timing jitter of 16 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half-rate CIL hybrid is only 2 mW, and its energy efficiency is 0.4 pJ/bit. The layout of the hybrid occupies an area of 0.0008 mm².

中文翻译：

一种用于芯片间互连全双工通信的高能效电流积分混合电路

这项工作提出了一种节能的半速率电流积分逻辑 (CIL) 回声消除混合电路拓扑，用于 65 nm CMOS 中片外互连的全双工通信。与传统的电流模式混合电路拓扑实现相比，所提出的混合拓扑具有低功耗，这要归功于具有采样和保持前端的 CIL 混合拓扑。半速率 CIL 混合电路的布局后性能包括封装寄生在 10 Gb/s 数据速率下具有 190 mV 的差分接收信号电压摆幅，在 20 cm FR4 PCB 互连上具有 16 ps 的定时抖动。半速率CIL混合的总功耗仅为2 mW，能量效率为0.4 pJ/bit。混合布局占地0.0008 mm ²。

更新日期：2022-07-27

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