The line edge roughness (LER) is one of the most dominant sources of variability in sub 10 nm technology node devices such as FinFET and Nanowire FET (NWFET). Earlier, analytical models of LER based threshold voltage ($V_T$) variability on FinFET have been comprehensively explored. However, the analytical modeling front for NWFET is still an open challenge. Specifically, the previous FinFET inspired analysis used a cross-sectional area-equivalent circular diameter as effective diameter ($D_{\mathit{eff}}$). The $D_{\mathit{eff}}$ defines the local $V_T$ for a cross-section that enables a percolation based $V_T$ estimation for the NWFET. In this work, we show that minimum local diameter ($D_{\mathit{min}}$) is a better predictor. $D_{\mathit{min}}$ captures the quantum confinement locally more accurately in the highly scaled NWFETs of interest to enable accurate percolation. The model is tested for LER infused NWFET structures and shows an excellent match against the well-calibrated Sentaurus TCAD deck with the RMS error less than 1.5 mV. The model is $5\times {10}^5$ times computationally efficient in comparison to conventional TCAD simulations. Moreover, the proposed $D_{\mathit{min}}$ based analytical model is 2.3× better in terms of accuracy and 10× faster as opposed to the state-of-the-art (i.e. $D_{\mathit{eff}}$ based model). Such analytical models can be integrated in BSIM CMG platform to enable device scaling study and its impact on circuit level performance predictions.

线边缘粗糙度 (LER) 是亚 10 纳米技术节点器件（例如 FinFET 和纳米线 FET (NWFET)）中最主要的可变性来源之一。早些时候，基于 LER 的阈值电压的分析模型（${五}_{吨}$) 对 FinFET 的可变性进行了全面探索。然而，NWFET 的分析建模前沿仍然是一个开放的挑战。具体来说，先前的 FinFET 启发分析使用横截面积等效圆直径作为有效直径（$D_{\mathit{效果}}$）。这$D_{\mathit{效果}}$定义本地${五}_{吨}$对于能够实现基于渗透的横截面${五}_{吨}$NWFET的估计。在这项工作中，我们证明了最小局部直径（$D_{\mathit{分钟}}$) 是一个更好的预测器。$D_{\mathit{分钟}}$在感兴趣的高度缩放的 NWFET 中更准确地局部捕获量子限制，以实现准确的渗透。该模型针对注入 LER 的 NWFET 结构进行了测试，并显示出与经过良好校准的 Sentaurus TCAD 平台的出色匹配，RMS 误差小于 1.5 mV。模型是$5\times {10}^5$与传统的 TCAD 仿真相比，计算效率高出数倍。此外，建议$D_{\mathit{分钟}}$与最先进的分析模型（即$D_{\mathit{效果}}$基于模型）。此类分析模型可以集成到 BSIM CMG 平台中，以实现器件缩放研究及其对电路级性能预测的影响。