This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of \(10^{-3}\).

本文提出了一种基于混合扩展最小和算法的NB-LDPC码的超高吞吐量解码器架构。我们引入了一个新的处理块，它以完全流水线的方式更新校验节点及其关联的变量节点，从而允许解码器在每个时钟周期处理一行奇偶校验矩阵。这项工作特别关注 GF(64) 上大小为 ( N , K ) = (144, 120) 个符号的速率 5/6 码。28 纳米技术的综合结果表明，对于 0.789 万与非门的复杂度，该架构通过 30 次解码迭代达到了 0.9 Gbps 的解码吞吐量。与相同大小和码率的 5G 二进制 LDPC 码相比，所提出的架构在帧误码率为 0.3 dB 时提供了增益。\(10^{-3}\)。