The back-gate terminal biasing has been used to improve the SRAM cells’ performance. In this paper, the impact of back-gate bias on the performance of 22 nm FDSOI SRAM 6T cell is analyzed. The cell is fabricated in the regular well and two back-gate terminals are connected to Pwell and Nwell, respectively. The influences of back-gate bias on the cell are studied by the variations of the metrics of leakage current, read current, static noise margin (SNM) and N-curve under the three back-gate bias combinations. Through measurements and HSPICE simulations, the mechanism of the variations of the cell metrics caused by the changes of the back-gate bias is explained by the shift of electrical characteristics of transistors inside the cell.

背栅端子偏置已用于提高 SRAM 单元的性能。本文分析了背栅偏压对22 nm FDSOI SRAM 6T单元性能的影响。该单元在常规阱中制造，两个背栅端子分别连接到 Pwell 和 Nwell。通过三种背栅偏压组合下漏电流、读取电流、静态噪声容限(SNM)和N曲线等指标的变化，研究了背栅偏压对单元的影响。通过测量和 HSPICE 模拟，由背栅偏置变化引起的单元指标变化的机制可以通过单元内晶体管的电气特性的变化来解释。