Metal-Insulator-Semiconductor micro-capacitors for on-chip energy storage were fabricated and characterized. The capacitors were based on Si nanowires fabricated by Metal Assisted Chemical Etching. 1.2 μm long nanowires with 100 nm average diameter were created leading to an effective area increase of 6.28, as compared to a flat surface. Nanowires were chemically treated to reduce surface roughness and electronic states and were coated by a HfO₂ layer, deposited by Atomic Layer Deposition, to act as the dielectric. Al and Cu were deposited as two possible top metal electrodes. The use of Al as the top electrode was shown to create a parasitic interface oxide between the metal and the dielectric, reducing the measured capacitance. The use of Cu was shown to significantly reduce this problem, leading to more efficient devices. Capacitors with 5.4 μF/cm² capacitance and 8.9 × 10⁻⁷ A/cm² leakage current at −2.5 V were demonstrated along with a cutoff frequency of 10⁴ Hz. These values make the demonstrated capacitors very attractive for on-chip energy storage applications.

制造并表征了用于片上储能的金属-绝缘体-半导体微电容器。电容器基于通过金属辅助化学蚀刻制造的硅纳米线。与平坦表面相比，产生了平均直径为 100 nm 的 1.2 μm 长纳米线，导致有效面积增加 6.28。纳米线经过化学处理以降低表面粗糙度和电子状态，并涂有 HfO ₂层，通过原子层沉积沉积，用作电介质。Al和Cu被沉积为两种可能的顶部金属电极。显示使用铝作为顶部电极会在金属和电介质之间产生寄生界面氧化物，从而降低测量的电容。使用 Cu 可以显着减少这个问题，从而产生更高效的设备。演示了具有 5.4 μF/cm ²电容和 -2.5 V 时的 8.9 × 10 ^-7  A/cm ^{2泄漏电流的电容器以及 10 4}  Hz的截止频率。这些值使展示的电容器对片上储能应用非常有吸引力。