Virtual FPGAs (V-FPGAs) are used as vendor-independent virtualization layers, to retrofit features which are not available on the host FPGA and to prototype novel FPGA architectures. In these usecases, the achievable clock frequencies of V-FPGA user applications are a major concern. The abstraction layer inherently induces overhead, but this aspect is reinforced by nonuniformity effects: When V-FPGA cells perform worse locally, basic architecture modeling generalizes these worst-case path delays to the whole device, limiting applications to a lower frequency than theoretically achievable. We propose three approaches to attenuate these effects: First we introduce uniformity metrics and manual V-FPGA placement strategies for more uniform placement, improving achievable frequency by 16 %. Second, we propose a framework for automated timing extraction, enabling individual characterization of each V-FPGA design. Third, after evaluating Vivado synthesis strategies, we extend the timing model for non-uniform timings, achieving improvements of up to 28 %.

虚拟 FPGA (V-FPGA) 用作独立于供应商的虚拟化层，以改进主机 FPGA 上不可用的功能，并原型化新颖的 FPGA 架构。在这些用例中，V-FPGA 用户应用程序可实现的时钟频率是一个主要问题。抽象层本质上会产生开销，但这一方面会因非均匀性效应而得到加强：当 V-FPGA 单元在本地性能较差时，基本架构建模会将这些最坏情况的路径延迟推广到整个设备，从而将应用程序限制在比理论上可实现的频率更低的频率。我们提出了三种方法来减弱这些影响：首先，我们引入了均匀性指标和手动 V-FPGA 布局策略，以实现更均匀的布局，将可实现的频率提高 16%。其次，我们提出了一个自动时序提取的框架，能够对每个 V-FPGA 设计进行单独表征。第三，在评估了 Vivado 综合策略后，我们针对非均匀时序扩展了时序模型，实现了高达 28% 的改进。