This work presents two novel methods that simultaneously optimize both the design of a finite impulse response (FIR) filter and its multiplierless hardware implementation. We use integer linear programming (ILP) to minimize the number of adders used to implement a direct/transposed FIR filter adhering to a given frequency specification. The proposed algorithms work by either fixing the number of adders used to implement the products (multiplier block adders) or by bounding the adder depth (AD) used for these products. The latter can be used to design filters with minimal AD for low-power applications. In contrast to previous multiplierless FIR filter approaches, the methods introduced here ensure adder count optimality. We perform extensive numerical experiments, which demonstrate that our simultaneous filter design approach yields results that are in many cases on par or better than those in the literature.

中文翻译：

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具有最少加法器数量的最优无乘法器 FIR 滤波器的设计


这项工作提出了两种新颖的方法，可同时优化有限脉冲响应 (FIR) 滤波器的设计及其无乘法器硬件实现。我们使用整数线性规划 (ILP) 来最大限度地减少用于实现符合给定频率规范的直接/转置 FIR 滤波器的加法器数量。所提出的算法通过固定用于实现乘积的加法器的数量（乘法器块加法器）或通过限制用于这些乘积的加法器深度（AD）来工作。后者可用于为低功耗应用设计具有最小 AD 的滤波器。与之前的无乘法器 FIR 滤波器方法相比，这里介绍的方法可确保加法器计数最优性。我们进行了广泛的数值实验，证明我们的同步滤波器设计方法产生的结果在许多情况下与文献中的结果相当或更好。