Processing-in-memory (PIM) architecture has been proposed to accelerate state-of-the-art neuro-inspired algorithms, such as deep neural networks. In this article, we present PIMulator-NN, an event-driven, cross-level simulation framework for PIM-based neural network accelerators. By employing an event-driven simulation mechanism, PIMulator-NN is able to model architecture details and capture design details of the architecture. Moreover, we integrate the main-stream circuit-level simulation framework with PIMulator-NN to accurately simulate the area, latency, and energy consumption of analog computation units. To demonstrate the usage of PIMulator-NN, we implement several PIM designs with PIMulator-NN and perform detailed simulation. The simulation results show that memory access and interconnects make considerable impacts on system-level performance and energy. Note that such results are hard to be captured by conventional performance model-based estimations. We found some anti common-sense results while modeling the architecture details with PIMulator-NN. With several architecture templates, PIMulator-NN provides the users with a platform to build up their PIM architecture quickly. PIMulator-NN is able to capture the impacts of different design choices (e.g., dataflow, interconnect, data parallelism, etc.), and this could enable users to explore their design space efficiently.

中文翻译：

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PIMulator-NN：用于基于内存处理的神经网络加速器的事件驱动的跨级仿真框架


内存处理 (PIM) 架构已被提出来加速最先进的神经启发算法，例如深度神经网络。在本文中，我们介绍 PIMulator-NN，这是一种用于基于 PIM 的神经网络加速器的事件驱动的跨级仿真框架。通过采用事件驱动的仿真机制，PIMulator-NN 能够对架构细节进行建模并捕获架构的设计细节。此外，我们将主流电路级仿真框架与PIMulator-NN集成，精确模拟模拟计算单元的面积、延迟和能耗。为了演示 PIMulator-NN 的用法，我们使用 PIMulator-NN 实现了多个 PIM 设计并进行了详细的仿真。仿真结果表明，内存访问和互连对系统级性能和能耗有相当大的影响。请注意，这样的结果很难通过传统的基于性能模型的估计来捕获。我们在使用 PIMulator-NN 进行架构细节建模时发现了一些反常识的结果。 PIMulator-NN 拥有多种架构模板，为用户提供快速构建 PIM 架构的平台。 PIMulator-NN 能够捕获不同设计选择（例如数据流、互连、数据并行性等）的影响，这可以使用户有效地探索其设计空间。