This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.

中文翻译：

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STT-BNN：用于二元神经网络的新型 STT-MRAM 内存计算宏


本文提出了一种基于 STT-MRAM 阵列的二进制神经网络 (BNN) 工作负载内存计算的新颖架构。在所提出的架构中，BNN 输入通过位线馈送，然后，可以通过单次感测行的合并 SL 电压来完成 BNN 向量乘法。我们的设计允许跨行执行无限制的累积，以充分利用阵列和 BNN 模型的可扩展性，并克服了由于 STT-MRAM 中规则隧道磁阻比 (TMR) 较低的限制而对传感电路造成的挑战。外围引入电路技术，使能量-速度-面积-鲁棒性的权衡更加有利。特别是，引入基于时间的传感 (TBS) 和 boosting 来提高 BNN 计算的准确性。系统模拟显示，在局部和全局过程变化的影响下，CIFAR-10 (MNIST) 数据集下的精度为 80.01% (98.42%)，与原始 BNN 软件实现相比，精度损失为 8.59% (0.38%)，同时实现能源效率为 311 TOPS/W。