Modern computing applications based upon machine learning can incur significant data movement overheads in state-of-the-art computers. Resistive-memory-based processing-using-memory (PUM) can mitigate this data movement by instead performing computation in situ (i.e., directly within memory cells), but device-level limitations restrict the practicality and/or performance of many PUM architecture proposals. The RACER architecture overcomes these limitations, by proposing efficient peripheral circuitry and the concept of bit-pipelining to enable high-performance, high-efficiency computation using small memory tiles. In this work, we extend RACER to adapt easily to different PUM logic families, by (1) modifying the device access circuitry to support a wide range of logic families, (2) evaluating three logic families proposed by prior work, and (3) proposing and evaluating a new logic family called OSCAR that significantly relaxes the switching voltage constraints required to perform logic with resistive memory devices. We show that the modified RACER architecture, using the OSCAR logic family, can enable practical PUM on real ReRAM devices while improving performance and energy savings by 30% and 37%, respectively, over the original RACER work.

中文翻译：

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采用 RACER 架构来集成改进的 In-ReRAM 逻辑原语


基于机器学习的现代计算应用程序可能会在最先进的计算机中产生大量的数据移动开销。基于电阻存储器的使用存储器的处理 (PUM) 可以通过原位执行计算（即直接在存储器单元内）来减轻这种数据移动，但设备级限制限制了许多 PUM 架构建议的实用性和/或性能。 RACER 架构克服了这些限制，提出了高效的外围电路和位流水线概念，以使用小内存块实现高性能、高效率的计算。在这项工作中，我们扩展 RACER 以轻松适应不同的 PUM 逻辑系列，方法是 (1) 修改器件访问电路以支持广泛的逻辑系列，(2) 评估先前工作提出的三个逻辑系列，以及 (3)提出并评估了一种名为 OSCAR 的新逻辑系列，该系列显着放宽了使用电阻式存储器件执行逻辑所需的开关电压限制。我们证明，使用 OSCAR 逻辑系列的修改后的 RACER 架构可以在真正的 ReRAM 设备上实现实用的 PUM，同时比原始 RACER 工作分别提高性能和节能 30% 和 37%。