Abstract We present a framework for the synthesis of phase polynomials that addresses both cases of full connectivity and partial connectivity for NISQ architectures. In most cases, our algorithms generate circuits with lower CNOT count and CNOT depth than the state of the art or have a significantly smaller running time for similar performances. We also provide methods that can be applied to our algorithms in order to trade an increase in the CNOT count for a decrease in execution time, thereby filling the gap between our algorithms and faster ones.

中文翻译：

---

用于 NISQ 架构及其他架构的相位多项式综合算法

摘要我们提出了一个综合相位多项式的框架，该框架解决了 NISQ 架构的完全连通性和部分连通性两种情况。在大多数情况下，我们的算法生成的电路具有比现有技术更低的 CNOT 计数和 CNOT 深度，或者具有显着更短的运行时间以获得类似的性能。我们还提供了可以应用于我们的算法的方法，以便用增加的 CNOT 计数来减少执行时间，从而填补我们的算法和更快的算法之间的差距。