ABSTRACT

In this paper, a delay efficient multi-operand adder (MOA) is introduced by considering the compression logic and variable latency carry skip adder (VL-CSKA). Here, an optimised 5:2 compressor is initially used to increase the speed of MOA by reducing the number of operands before giving as input to VL-CSKA. Also, the VL-CSKA is modified by replacing the carry propagation with complementary complex gates (CCG) and nucleus stage with improved parallel prefix structure for increasing the speed with fewer components. The delay, area, power and logic depth of the proposed hybrid parallel prefix VL-CSKA (HPP-VL-CSKA) is also reduced by modifying the group Propagate–Generate (PG) logic in the parallel prefix structure. Also, a new circuit for XOR/XNOR gate is used for the reduction of the delay and power consumption significantly. The synthesis result shows that the suggested adder design overtakes the existing adders by consuming only 5953µm² area, 1.763mW power, 1.251fJ and 3516.63 ADP for 20 number of operands, each with 32 bit inputs.

摘要

在本文中，通过考虑压缩逻辑和可变延迟进位跳跃加法器（VL-CSKA），引入了延迟高效的多操作数加法器（MOA）。在这里，优化的 5:2 压缩器最初用于通过在作为输入提供给 VL-CSKA 之前减少操作数的数量来提高 MOA 的速度。此外，对 VL-CSKA 进行了修改，用互补复杂门 (CCG) 代替进位传播，用改进的并行前缀结构代替核级，以用更少的组件提高速度。所提出的混合并行前缀 VL-CSKA (HPP-VL-CSKA) 的延迟、面积、功率和逻辑深度也通过修改并行前缀结构中的组传播-生成 (PG) 逻辑来减少。此外，新的 XOR/XNOR 门电路用于显着降低延迟和功耗。^{2 个}区域，1.763mW 功率，1.251fJ 和 3516.63 ADP，用于 20 个操作数，每个操作数有 32 位输入。