A sub-sampling PLL (SSPLL) employing an adaptive frequency-locked loop (FLL) without static power consumption is proposed in this letter. A new unlock detection mechanism and a configurable PFD are realized in the adaptive FLL. With the new unlock detection mechanism, while the FLL that contains phase detector, divider, and charge pump dissipates no power during the locked steady state, it automatically starts when external interferences disturb the locked state. The optimized dead zone in the configurable PFD ensures a rapid relocking operation. Based on the proposed adaptive FLL, the 2.4 GHz SSPLL is fabricated in a 40-nm CMOS process. It achieves −128.5 dBc/Hz at 1 MHz offset frequency and the rms jitter is 103.58 fs integrated from 10 k to 10 MHz. It consumes 1.55 mW at 1 V supply and achieves −257.8 dB FOM.

中文翻译：

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具有自适应且无功率贡献 FLL 的 2.4GHz 子采样 PLL，可实现 103.58 fs rms 抖动和 257.8 dB FOM


本文提出了一种采用自适应锁频环 (FLL) 且无静态功耗的子采样 PLL (SSPLL)。自适应FLL 中实现了新的解锁检测机制和可配置的PFD。凭借新的解锁检测机制，虽然包含鉴相器、分频器和电荷泵的FLL在锁定稳定状态期间不耗电，但当外部干扰扰乱锁定状态时，它会自动启动。可配置 PFD 中的优化死区可确保快速重新锁定操作。基于所提出的自适应 FLL，2.4 GHz SSPLL 采用 40 nm CMOS 工艺制造。它在 1 MHz 偏移频率下实现了 −128.5 dBc/Hz，并且从 10 k 到 10 MHz 的积分均方根抖动为 103.58 fs。它在 1 V 电源电压下消耗 1.55 mW，并实现 −257.8 dB FOM。