A phase-locked loop (PLL) cascade driven by a crystal oscillator and a free running dielectric resonator oscillator (DRO) is proposed. For minimizing phase noise, spurious tones and jitter, a programmable PLL1 in the lower GHz range is used to drive a millimeter-wave (mmW) PLL2 with a fixed frequency multiplication factor. The phase noise analysis results in two optimum bandwidths of the two PLLs for the lowest output jitter of the cascade. Phase noise and spurious tones (spurs) in PLL1 are further reduced by dividing the output frequency of PLL1 and up-converting it by means of a single-sideband (SSB) mixer driven by the DRO. By including the SSB mixer in the feedback loop of PLL1 manual tuning of the DRO is avoided, and a low-noise free running DRO can be employed. An exemplary design in SiGe BiCMOS technology is presented.

中文翻译：

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一种用于低抖动多 GHz 频率合成的新型架构

提出了一种由晶体振荡器和自由运行的介质谐振器振荡器（DRO）驱动的锁相环（PLL）级联。为了最大限度地减少相位噪声、杂散音和抖动，较低 GHz 范围内的可编程 PLL1 用于驱动具有固定倍频因子的毫米波 (mmW) PLL2。相位噪声分析导致两个 PLL 的两个最佳带宽，以实现级联的最低输出抖动。通过对 PLL1 的输出频率进行分频并通过 DRO 驱动的单边带 (SSB) 混频器对其进行上变频，可以进一步降低 PLL1 中的相位噪声和杂散音（杂散）。通过在 PLL1 的反馈回路中包含 SSB 混频器，避免了 DRO 的手动调谐，并且可以采用低噪声无运行 DRO。介绍了 SiGe BiCMOS 技术中的示例性设计。