Several authorsinvestigated the use of internal digital communication networks in Modular Multilevel Converters. The first works in this area keep a centralized control scheme, but they struggle to reach the fast cycle times required for achieving goodcontrol performance, specially as the number of cells increases. To reduce the network cycle time, some authors adopted a partly decentralized control scheme. However, those proposals restrict the capacitorbalancing to a closed-loop strategy and the use of carrier-based modulation. This work introduces DiSortNet, a novel Ethernet-based ring network protocol that achieves low cycle times while preserving the centralized control scheme and its modulation flexibility. DiSortNet emerges from a communications-control co-design approach, which main feature is the distributed sorting of capacitor voltages. We show that distributed sorting implies a marginal degradation in the balancing of capacitor voltages while bounding the network payload and reducing the cycle time. Implementation-wise, using FPGA-based network interfaces, DiSortNet achieves half the cycle-time obtained with EtherCAT in a network with 86 nodes and less than half for larger networks, reaching 157 μs with 300 nodes.

中文翻译：

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DiSortNet：用于模块化多级转换器的分布式排序网络协议


几位作者研究了内部数字通信网络在模块化多电平转换器中的使用。该领域的第一个工作保留了集中控制方案，但它们很难达到实现良好控制性能所需的快速循环时间，特别是当电池数量增加时。为了减少网络循环时间，一些作者采用了部分分散的控制方案。然而，这些建议将电容器平衡限制为闭环策略和基于载波的调制的使用。这项工作介绍了 DiSortNet，这是一种基于以太网的新型环网协议，可实现低循环时间，同时保留集中控制方案及其调制灵活性。 DiSortNet源自通信控制协同设计方法，其主要特点是电容器电压的分布式排序。我们表明，分布式排序意味着电容器电压平衡的边际退化，同时限制了网络有效负载并减少了周期时间。在实现方面，使用基于 FPGA 的网络接口，DiSortNet 在具有 86 个节点的网络中实现了 EtherCAT 的一半周期时间，而对于较大的网络则不到一半，在 300 个节点时达到 157 μs。