ABSTRACT

In this paper, a multi-digit ternary (multi-trit) Wallace tree-based multiplier in CNTFET technology is presented. In this work, a modified 1-trit multiplier is applied to reduce the number of the CNTFETs where it uses unary operators to estimate the product and the carry. An optimised architecture of a multi-digit ternary adder is also presented. It is applied at the last stage of the multiplier to reduce the overall propagation delay. Hence, higher speed is achieved spending a few more number of CNTFETs. The proposed design is simulated in HSPICE using Stanford University’s 32 nm CNFET technology model. Simulation results show significant improvements in power delay products and hardware utilisation. The proposed 3-trit multiplier applies 750 number of CNTFETs where the PDP is 75 fJ. This represents an approximately 20% improvement in the PDP while more than 100 CNTFETs are saved. For further evaluation, the proposed structure is also extended to 6, 9 and 12-trit multipliers.

摘要

在本文中，提出了一种采用 CNTFET 技术的多位数三元 (multi-trit) Wallace 树基乘法器。在这项工作中，应用修改后的 1-trit 乘法器来减少 CNTFET 的数量，其中它使用一元运算符来估计乘积和进位。还介绍了多位数三进制加法器的优化架构。它应用于乘法器的最后一级，以减少整体传播延迟。因此，使用更多数量的 CNTFET 可以实现更高的速度。拟议的设计在 HSPICE 中使用斯坦福大学的 32 nm CNFET 技术模型进行仿真。仿真结果显示功率延迟产品和硬件利用率有了显着改善。提议的 3-trit 乘法器应用 750 个 CNTFET，其中 PDP 为 75 fJ。这表示 PDP 提高了大约 20%，同时节省了 100 多个 CNTFET。为了进一步评估，建议的结构也扩展到 6、9 和 12-trit 乘法器。