This article presents a pulse-amplitude-modulated (PAM)-8 wireline transceiver with receiver-side pulsewidth-modulated (PWM) or time-domain-based feedforward equalization (FFE) technique. The receiver converts the voltage-modulated signals or PAM signals into PWM signals and processes them using inverter-based delay elements having a rail-to-rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 to 39.6 Gb/s and compensates 14-dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65-nm CMOS.

中文翻译：

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采用线性度改进技术和 65 nm CMOS 中时域接收器侧 FFE 的 PAM-8 有线收发器


本文介绍了一种采用接收器侧脉宽调制 (PWM) 或基于时域的前馈均衡 (FFE) 技术的脉冲幅度调制 (PAM)-8 有线收发器。接收器将电压调制信号或 PAM 信号转换为 PWM 信号，并使用具有轨到轨电压摆幅的基于逆变器的延迟元件对其进行处理。时间-电压和电压-时间转换器被设计为具有相反符号的非线性，目的是在接收器上实现更高的前端线性度。拟议的 PAM-8 收发器可以在 12.0 至 39.6 Gb/s 范围内运行，并在 6.6 GHz 下补偿 14 dB 损耗，在 65 nm CMOS 中效率为 8.66 pJ/位。