ABSTRACT

Rapidly growing technology has increased the demand for digital signal processing applications that are fast and effective in real-time. One of the basic operations frequently required in these applications is the multiplication operation. There is a need to develop a multiplier with high speed, less area, and low power consumption to improve its performance. One of the fastest multiplier circuits is the Radix-4 Booth multiplier. Booth encoder reduces the number of partial products and hence the number of additions. The pipeline scheme is one of the most used designs to accelerate the multiplier performance. In this paper, two designs are presented. The first proposed design aims to reduce the delay of the multiplication operation of a 16 × 16 multiplier. This design uses a pipeline scheme differently by partitioning the input into two parts and overlapping their processing. The second proposed design reduces the multiplier area by applying enhancements in the modified booth encoder circuit. The proposed circuits are synthesized using XILINX ISE 14.7 and realized using ML605 Virtex 6 FPGA board. The first proposed design achieves higher speed, lower power consumption, and less area than the prior design. The second proposed design achieves more area and power consumption reduction.

摘要

快速发展的技术增加了对实时快速有效的数字信号处理应用程序的需求。这些应用程序中经常需要的基本运算之一是乘法运算。需要开发一种速度快、面积小、功耗低的乘法器来提高其性能。最快的乘法器电路之一是 Radix-4 Booth 乘法器。Booth 编码器减少了部分产品的数量，因此减少了添加的数量。流水线方案是最常用的加速乘法器性能的设计之一。在本文中，提出了两种设计。第一个提出的设计旨在减少 16 × 16 乘法器的乘法运算延迟。此设计通过将输入分成两部分并重叠它们的处理来使用不同的流水线方案。第二个提议的设计通过在改进的 booth 编码器电路中应用增强功能来减少乘法器面积。建议的电路使用 XILINX ISE 14.7 进行综合，并使用 ML605 Virtex 6 FPGA 板实现。与之前的设计相比，第一个提出的设计实现了更高的速度、更低的功耗和更小的面积。第二个提议的设计实现了更多的面积和功耗减少。与之前的设计相比，功耗更低，面积更小。第二个提议的设计实现了更多的面积和功耗减少。与之前的设计相比，功耗更低，面积更小。第二个提议的设计实现了更多的面积和功耗减少。