In this article, we present static random access memory (SRAM) write- and performance-assist cells (W- and P-ACs, respectively) that can effectively resolve the degradation in writeability and performance due to the increase in interconnect resistance with technology scaling. The proposed W- and P-ACs have bit-cell compatible layouts, and thus, they can be inserted into a bit-cell array without white space. Given that bit-line (BL) and BL-bar (BLB) are driven in parallel by the write driver (WD) and proposed W-AC, the effective BL resistance (RBL(R_{\mathbf {BL}} ) is reduced. This, in turn, leads to an improvement in writeability. In addition, the proposed P-AC accelerates word-line (WL) by sensing WL rising voltage and, thus, improves the read access time on the bit-cell located far from the WL driver. To measure the interconnect resistance effects, 32-kb SRAM macros with poly resistors were fabricated on 28-nm CMOS technology. The proposed W-AC achieves 100% writeability yield not only in the 3-nm resistance model but also in the sub-3-nm resistance model, while the writeability yield of the conventional scheme with a single WD decreased to 2.3σ2.3\sigma in the 3-nm resistance model. The proposed P-AC reduced the read access time by 28% compared with that of the conventional scheme with a single WL driver in the 3-nm resistance model.

中文翻译：

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SRAM 写入和性能辅助单元可减少随着技术扩展而增加的互连电阻效应


在本文中，我们提出了静态随机存取存储器 (SRAM) 写入辅助单元和性能辅助单元（分别为 W-AC 和 P-AC），它们可以有效解决由于技术扩展导致互连电阻增加而导致的可写性和性能下降问题。所提出的 W-AC 和 P-AC 具有位单元兼容的布局，因此，它们可以插入到没有空白的位单元阵列中。假设位线 (BL) 和 BL-bar (BLB) 由写入驱动器 (WD) 并行驱动并提出 W-AC，则有效 BL 电阻 (RBL(R_{\mathbf {BL}} ) 会降低此外，所提出的 P-AC 通过感测 WL 上升电压来加速字线 (WL)，从而改善远离位单元的读取访问时间。为了测量互连电阻效应，采用 28 nm CMOS 技术制造了带有多晶硅电阻器的 32 kb SRAM 宏，所提出的 W-AC 不仅在 3 nm 电阻模型中实现了 100% 的可写率。亚3纳米电阻模型中，单个WD的传统方案的可写率在3纳米电阻模型中下降至2.3σ2.3\sigma，所提出的P-AC将读取访问时间减少了28%。与 3 nm 电阻模型中具有单个 WL 驱动器的传统方案进行比较。