Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.

中文翻译：

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高吞吐量非二进制 LDPC 解码器调查：ASIC、FPGA 和 GPU 架构


当码字长度适中和/或信道存在突发错误时，非二进制低密度奇偶校验（NB-LDPC）码比二进制低密度奇偶校验（LDPC）码表现出更高的纠错性能。未来数字通信对高速解码器的需求导致了对优化 NB-LDPC 解码算法和针对高吞吐量和低能耗水平的高效实现的研究。我们对现有的 NB-LDPC 解码硬件进行了全面调查，旨在优化这些参数。尽管现有的 NB-LDPC 解码器在计算复杂性和内存要求方面进行了优化，但它们在吞吐量、功耗和面积优化方面仍然落后于二进制解码器。这项研究有助于全面了解基于专用集成电路 (ASIC)、现场可编程门阵列 (FPGA) 和图形处理单元 (GPU) 的系统的最新技术，并强调当前的挑战在通往更高效的 NB-LDPC 解码器架构的道路上仍然需要克服这些问题。