A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [19]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [42], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under ⁸⁴Kr¹⁷⁺ exposure of 322.0 MeV at various flux condition from 1 × 10³ to 5 × 10⁵ count/cm²/sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage.

高速有线接口，例如 LVDS（低压差分信号），广泛用于航空航天领域，用于人造卫星和飞机的强大计算 [19]。本文介绍了数据发射机设计阶段辐照环境下有线数据传输的误码率（BER）预测方法，有助于主动判断设计电路是否满足目标系统的误码率标准。使用定制设计的 LVDS 发射器 (TX) 来增强抗闩锁能力 [42]，分析了晶体管尺寸和 BER 之间的关系，重点关注单事件效应 (SEE) 作为比特错误的原因。测量是在322.0 MeV 的⁸⁴ Kr ¹⁷⁺暴露下在 1 × 10³至 5 × 10 ^{5 个}/cm ²/sec 使用回旋加速器设施。为了分析误码，利用SPICE的电路仿真，并通过电流源模型表达辐照环境。电流源模型表示在体 MOSFET 的漏极和衬底结处对电路的单个事件冲击。为了构建电流源模型，通过为体晶体管工艺技术的 MOS 器件创建 3D 技术 CAD (TCAD) 模型，模拟了单粒子撞击时的电荷收集。将电荷校正的仿真结果转化为一个简单的时域方程，并利用该方程生成单事件电流源模型。单事件电流源应用于 LVDS 发送器中偏置电流相关电路的 SPICE 仿真，然后仔细验证仿真结果是否输出数据受到足够的干扰而导致有线数据传输的误码。通过模拟，已指定敏感 MOSFET，并且与实际 BER 测量相比，这些 MOSFET 的栅极面积总和的相关性比正常评估指标（漏极面积总和）好 29%。通过使用当前模型的 SPICE 仿真精确揭示敏感区域，可以在预制设计阶段估计辐照环境下的 BER。敏感 MOSFET 已被指定，与实际 BER 测量相比，这些 MOSFET 的栅极面积总和的相关性比正常评估指数（漏极面积总和）好 29%。通过使用当前模型的 SPICE 仿真精确揭示敏感区域，可以在预制设计阶段估计辐照环境下的 BER。敏感 MOSFET 已被指定，与实际 BER 测量相比，这些 MOSFET 的栅极面积总和的相关性比正常评估指数（漏极面积总和）好 29%。通过使用当前模型的 SPICE 仿真精确揭示敏感区域，可以在预制设计阶段估计辐照环境下的 BER。