Abstract

In modern microprocessors, the arithmetic logic units (ALUs) with the accelerated transfer organization, which are faster than ALUs with the sequential organization of arithmetic transfer, are widely used to reduce time costs. However, as the input data capacity increases, the operating time of such ALUs increases linearly with an increase in the number of bits. Developing an efficient ALU to deliver better performance than the existing known solutions is a pressing challenge. In this study, ALUs with the sequential and accelerated organization of arithmetic transfer are analyzed. A multidigit ALU is developed to increase the operating speed. All the ALU schemes were modeled in the CAD Altera Quartus-II environment. The number of gates and the maximum delay in the ALU circuit simulation report are compared for 4, 8, 16, 32, and 64 bits. A results verification scheme is implemented to confirm the reliability of the developed ALU. It is found that when performing operations with 64-bit operands, the developed ALU reduces the maximum delay by 53% compared to ALUs with the sequential organization of the arithmetic transfer and by 35.5% compared to ALUs with the accelerated organization of the arithmetic transfer.

中文翻译：

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提高多位算术逻辑单元的性能

摘要

在现代微处理器中，具有加速传输组织的算术逻辑单元（ALU）比具有算术传输顺序组织的ALU更快，被广泛用于减少时间成本。然而，随着输入数据容量的增加，这种 ALU 的操作时间随着位数的增加而线性增加。开发高效的 ALU 以提供比现有已知解决方案更好的性能是一项紧迫的挑战。在这项研究中，分析了具有算术传输顺序和加速组织的 ALU。开发了多位 ALU 以提高操作速度。所有 ALU 方案都在 CAD Altera Quartus-II 环境中建模。ALU 电路仿真报告中的门数和最大延迟比较了 4、8、16、32 和 64 位。实施结果验证方案以确认开发的 ALU 的可靠性。结果表明，在使用 64 位操作数进行运算时，所开发的 ALU 与具有算术传输顺序组织的 ALU 相比减少了 53% 的最大延迟，与具有算术传输加速组织的 ALU 相比减少了 35.5%。