Abstract

The Boolean satisfiability (SAT) methods are one of the efficient approaches used to solve the problems of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, these methods demonstrate better results than the classic routing algorithms in terms of the speed of operation and the quality of the results. In this paper, the modern practice of using the SAT methods in computer-aided design systems for VLSI is analyzed. The examples of modern SAT approaches to the problems of routing and the formal equivalence checking of digital circuits’ descriptions within the technological mapping as a part of the FPGA design flow are considered. The algorithm of the detailed routing of the FPGA switching blocks using the satisfiability problem is developed and presented. The results of its work are demonstrated on the example of the programmable logic block of the integrated circuit 5400TP094 made in Russia. The block has the island architecture, where the configurable logic blocks and switching blocks form a regularly repeated layout template. The properties of the chosen classic architecture allow us to expand the region of the presented algorithm to the entire class of island style of FPGA. The algorithm is tested on the project benchmarks ISCAS-85, ISCAS-89, and LGSynth-89. The comparison of the developed SAT-based algorithm with the well-known routing algorithm Pathfinder is presented by the criteria of the elapsed time and the achieved degree of routed nets in the switching blocks. It is specified that the considered Boolean satisfiability methods for the routing problem are capable to prove the circuit’s unroutability, unlike the Pathfinder algorithm whose results can only implicitly indicate it. The paper demonstrates that the application of a more efficient SAT solver significantly accelerates the work of the suggested detailed routing algorithm.

中文翻译：

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微电子学中现代计算机辅助设计问题的布尔可满足性方法

摘要

布尔可满足性(SAT)方法是用于解决数字电路的布尔匹配和等效性检查问题的有效方法之一。结合经典路由算法和优化技术，这些方法在运算速度和结果质量方面均优于经典路由算法。在本文中，分析了在 VLSI 计算机辅助设计系统中使用 SAT 方法的现代实践。作为 FPGA 设计流程的一部分，我们考虑了现代 SAT 方法解决路由问题和技术映射中数字电路描述的形式等效性检查的示例。开发并提出了使用可满足性问题的 FPGA 开关块详细布线算法。其工作结果以俄罗斯制造的集成电路5400TP094的可编程逻辑块为例进行了说明。该块具有孤岛架构，其中可配置的逻辑块和切换块形成一个有规律重复的布局模板。所选经典架构的特性使我们能够将所提出算法的区域扩展到整个 FPGA 岛式类型。该算法在项目基准 ISCAS-85、ISCAS-89 和 LGSynth-89 上进行了测试。所开发的基于 SAT 的算法与众所周知的路由算法 Pathfinder 的比较是通过经过时间的标准和交换块中路由网络的实现程度来呈现的。指定路由问题所考虑的布尔可满足性方法能够证明电路的不可路由性，不像探路者算法的结果只能隐含地表明它。该论文表明，更高效的 SAT 求解器的应用显着加快了建议的详细路由算法的工作。