In this paper, a method for maximum fault coverage with minimum power dissipation, during the testing of analog and digital circuits of mixed-signal System-on-Chip (SOC) simultaneously using Genetic Algorithm, (GA) is proposed. Mixed-signal SOC consists mainly of an analog block, a digital block and a DAC/ADC (Digital to Analog Converter/Analog to Digital Converter). Due to the presence of analog and digital circuits in mixed-signal SOCs, the testing procedure is difficult from that of only analog or digital circuit testing. Here stuck at 0/1 faults are considered for digital circuits, and stuck open/short faults are considered for analog circuits. In analog testing fault modeling, fault injection and fault simulation are done. The outputs of the analog block and some independent digital signals are given to the digital block. The GA-based approach is used for power-aware ordering of test patterns considering pattern dependency on previous patterns at the input of digital block as input patterns. The effect of noise on analog test signals has also been investigated here with the area analysis of the circuit. An average of 92.43% fault coverage and 13.56% maximum power saving is achieved when this methodology is applied to ITC 97 (Analog block) and ISCAS 85 (Digital block) benchmark circuits, respectively. A trade-off between fault coverage and power dissipation has been presented.

在本文中，提出了一种在同时使用遗传算法 (GA) 测试混合信号片上系统 (SOC) 的模拟和数字电路期间以最小功耗实现最大故障覆盖率的方法。混合信号SOC主要由模拟块、数字块和DAC/ADC（数模转换器/Analog to Digital Converter）组成。由于混合信号SOC中存在模拟和数字电路，因此测试过程比仅模拟或数字电路测试困难。这里卡在 0/1 故障是针对数字电路考虑的，卡在开路/短路故障是针对模拟电路考虑的。在模拟测试故障建模中，进行了故障注入和故障模拟。模拟块的输出和一些独立的数字信号被提供给数字块。基于 GA 的方法用于测试模式的功率感知排序，考虑模式对数字块输入处先前模式的依赖性作为输入模式。此处还通过电路面积分析研究了噪声对模拟测试信号的影响。将此方法分别应用于 ITC 97（模拟块）和 ISCAS 85（数字块）基准电路时，平均可实现 92.43% 的故障覆盖率和 13.56% 的最大节电。已经提出了故障覆盖率和功耗之间的权衡。当该方法分别应用于 ITC 97（模拟块）和 ISCAS 85（数字块）基准电路时，可实现 43% 的故障覆盖率和 13.56% 的最大节电。已经提出了故障覆盖率和功耗之间的权衡。将此方法分别应用于 ITC 97（模拟块）和 ISCAS 85（数字块）基准电路时，可实现 43% 的故障覆盖率和 13.56% 的最大节电。已经提出了故障覆盖率和功耗之间的权衡。