Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies.

基于二维 (2D) 材料的场效应晶体管具有用于超大规模集成 (VLSI) 技术的潜力，但它们是否可以用于线前端或线后端单片或异构集成仍有待确定。为此，必须克服多重挑战，包括降低接触电阻、开发稳定可控的掺杂方案、推进迁移率工程和提高高κ电介质集成。还需要均匀二维层的大面积生长，以确保低缺陷密度、低器件间差异和清洁界面。在这里，我们回顾了用于未来 VLSI 技术的 2D 场效应晶体管的发展。我们考虑了积极缩放的 2D 晶体管的关键性能指标，并讨论了如何提取和报告这些指标。我们还重点介绍了 2D 晶体管在传统微/纳米电子学、神经形态计算、先进传感、数据存储和未来互连技术中的潜在应用。