This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- NN phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional- NN mode, a phase detector range reduction technique is used to halve the required DTC delay range (DR), resulting in lower thermal noise and better DTC linearity. Moreover, a reconfigurable dual-core voltage-controlled oscillator (VCO) provides extra freedom in power and jitter tradeoff. It achieves 83.4-fs rms jitter in fractional- NN mode, integrated from 10 kHz to 100 MHz, with a 76.8-MHz crystal oscillator (XO) reference. In the low-power mode, the rms jitter degrades to 96.3 fs and the PLL FoM improves from −250.1 to −251.2 dB, as the PLL power consumption reduces from 14.2 to 8.2 mW. The measured fractional spurs are less than −70 dBc for near-integer channels. The PLL rms jitter remains within 100 fs across the 5–7-GHz output frequency band, thanks to the digital background calibrations. It is implemented in a 14-nm FINFET process and occupies 0.31 mm2.

中文翻译：

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使用 DTC 范围缩减技术和可重配置双核 VCO 的 14 nm 超低抖动分数 N PLL


这项工作提出了一种 6 GHz 低抖动和高品质因数 (FoM) 小数 NN 锁相环 (PLL)。它采用基于数字时间转换器 (DTC) 的采样 PLL 架构。为了在分数 NN 模式下实现超低抖动，使用相位检测器范围缩小技术将所需的 DTC 延迟范围 (DR) 减半，从而实现更低的热噪声和更好的 DTC 线性度。此外，可重新配置的双核压控振荡器 (VCO) 在功耗和抖动权衡方面提供了额外的自由度。它在小数 NN 模式下实现了 83.4fs rms 抖动，集成了 10kHz 至 100MHz 的频率以及 76.8MHz 晶体振荡器 (XO) 基准。在低功耗模式下，随着 PLL 功耗从 14.2 mW 降低至 8.2 mW，均方根抖动降低至 96.3 fs，并且 PLL FoM 从 -250.1 dB 改善至 -251.2 dB。对于近整数通道，测得的分数杂散小于 -70 dBc。得益于数字背景校准，PLL rms 抖动在 5–7 GHz 输出频带内保持在 100 fs 以内。它采用 14 nm FINFET 工艺实现，占地 0.31 mm2。