This article presents a 71–86 GHz 16-element array receiver application-specified integrated circuit (ASIC) for Massive multiple-input–multiple-output (MIMO) wireless uplink, featuring a multiple-output analog beamformer (BF) supporting up to 16 spatially multiplexed users at the same time. The ASIC includes 16 direct-conversion mixer-first RX front-ends, local oscillator (LO) generation and distribution, and a 16×1616\times 16 fully connected baseband analog beamformer, which derives each user stream as a linear combination of all the 16 antennas. The 16 mm2 28 nm CMOS ASIC is packaged on an organic interposer including a linear patch antenna array. Over-the-air measurements demonstrate up to 2 Gb/s single-user data-rate, and four simultaneous links at 500 Mb/s each, with number of users and data rate only limited by setup constraints. Circuits are optimized for low power consumption in order to enable scaling to massive arrays, and consumes 1.7 W total power, for a power figure of 7 mW/antenna/user.

中文翻译：

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用于大规模 MIMO 的 71 至 86 GHz 16 元件 x 16 波束多用户波束成形集成接收器子阵列


本文介绍了一款用于大规模多输入多输出 (MIMO) 无线上行链路的 71–86 GHz 16 元件阵列接收器专用集成电路 (ASIC)，具有支持多达 16 个单元的多输出模拟波束形成器 (BF)。同时空间复用用户。该 ASIC 包括 16 个直接转换混频器优先的 RX 前端、本地振荡器 (LO) 生成和分配，以及一个 16×1616×16 全连接基带模拟波束形成器，该波束形成器将每个用户流导出为所有用户流的线性组合。 16 根天线。 16 mm2 28 nm CMOS ASIC 封装在包括线性贴片天线阵列的有机中介层上。无线测量显示单用户数据速率高达 2 Gb/s，并且有四个同步链路，每个链路的速率为 500 Mb/s，用户数量和数据速率仅受设置限制。电路针对低功耗进行了优化，以便能够扩展到大规模阵列，总功耗为 1.7 W，每个天线/用户的功耗为 7 mW。