In recent times the double gate In_0.53Ga_0.47As/InP heterostructure MOSFET offers excellent electrostatic/RF performance in comparison with conventional Si-bulk MOSFET. Drain capacitance of DG-MOSFETs are mostly dominated by overlap capacitance due to the reduction junction capacitance and this can be minimized by inserting an underlap area between the source and drain region. Further, source side underlap contributes substantial deterioration of On current and increased threshold voltage variation. So, to overcome this problem, a high K spacer is introduced in the drain side of the gate region which reduces the parasitic capacitance without hampering the On current. This works investigates the impact of drain side spacer underlap on stepped poly gate In_0.53Ga_0.47As/InP asymmetric heterostructure (ASSH) double-gate (DG) MOSFET to improve the device performance. In the proposed model the poly gate splits into three steps with an expansion of gate oxide width from the source region to the drain region. So ASSH-DG MOSFET exhibits the exceptional benefits mainly owing to, (a) the reduced oxide thickness at the source, which results in a good electrostatic gate control along the channel, (b) the larger oxide thickness near the drain lowering the gate-to-drain capacitance, henceforth there is an improvement of On resistance $\left(R_{On}\right)$ in the linear region. The device performance metrics are examined using a 2D TCAD device simulator by considering the underlap length ranging from 0 nm to 8 nm with a step of 2 nm. Simulated results show ASSH-DG MOSFET exhibits a significant improvement of analog /RF parameters as compared to conventional hetero (H)-DG MOSFET.

最近，与传统的硅体 MOSFET 相比，双栅极 In _0.53 Ga _0.47 As/InP 异质结构 MOSFET 具有出色的静电/RF 性能。由于结电容的减少，DG-MOSFET 的漏极电容主要由重叠电容决定，这可以通过在源极和漏极区域之间插入一个欠重叠区域来最小化。此外，源极侧欠重叠导致导通电流的显着恶化和阈值电压变化的增加。因此，为了克服这个问题，在栅极区域的漏极侧引入了一个高 K 间隔层，它可以在不影响导通电流的情况下降低寄生电容。这项工作研究了漏极侧间隔物欠重叠对阶梯式多晶硅栅极 In _0.53 Ga的影响_0.47 As/InP 不对称异质结构 (ASSH) 双栅极 (DG) MOSFET，以提高器件性能。在所提出的模型中，多晶硅栅极分为三个步骤，栅极氧化物宽度从源极区域扩展到漏极区域。因此 ASSH-DG MOSFET 表现出非凡的优势，主要是因为，(a) 源极处的氧化物厚度减少，这导致沿沟道的静电栅极控制良好，(b) 漏极附近较大的氧化物厚度降低了栅极 -漏极电容，此后导通电阻有所改善$\left(R_{欧n}\right)$在线性区。通过考虑从 0 nm 到 8 nm 的欠重叠长度，步长为 2 nm，使用 2D TCAD 设备模拟器检查设备性能指标。模拟结果表明，与传统的异质 (H)-DG MOSFET 相比，ASSH-DG MOSFET 的模拟/RF 参数有了显着改善。