This paper proposes a new finite precision iterative decoder for low-density parity-check (LDPC) codes. The proposed decoder, named Sign-Preserving Min-Sum (SP-MS), significantly improves the decoding performance compared to the classical Offset Min-Sum (OMS) decoder when messages are quantized on q=2q=2 , 3, or 4 bits. The particularity of the SP-MS decoder is that messages cannot take the 0 value, and can fully benefit from the qq bits of precision. The optimization of the SP-MS decoder is investigated in the asymptotic limit of the code length using density evolution (DE). Our study shows that 3-bit SP-MS decoders can achieve the same error-correcting performance as 5-bit OMS decoders, and 2-bit SP-MS decoders outperform 3-bit OMS decoders. The finite-length simulations confirm the conclusions of the DE analysis for several LDPC codes. Our SP-MS decoder shows a signal-to-noise ratio (SNR) gain up to 0.43 dB, with a memory/wire reduction of up to 40%, compared to the OMS decoder. Moreover, the SP-MS decoder converges faster and uses fewer iterations than the OMS decoder, with an improvement of up to 83.3% of the average decoding throughput. On an FPGA, the SP-MS decoder reduces resource utilization by up to 56% compared to the OMS decoder.

中文翻译：

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符号保留最小和解码器


本文提出了一种新的低密度奇偶校验（LDPC）码的有限精度迭代解码器。当消息在 q=2q=2、3 或 4 位上量化时，所提出的解码器称为符号保留最小和 (SP-MS)，与经典的偏移最小和 (OMS) 解码器相比，显着提高了解码性能。 SP-MS解码器的特殊性在于消息不能取0值，并且可以充分受益于qq位的精度。使用密度演化（DE）在码长渐近极限下研究了 SP-MS 解码器的优化。我们的研究表明，3 位 SP-MS 解码器可以实现与 5 位 OMS 解码器相同的纠错性能，并且 2 位 SP-MS 解码器优于 3 位 OMS 解码器。有限长度模拟证实了几种 LDPC 码的 DE 分析结论。与 OMS 解码器相比，我们的 SP-MS 解码器的信噪比 (SNR) 增益高达 0.43 dB，内存/线路减少高达 40%。此外，与 OMS 解码器相比，SP-MS 解码器收敛速度更快，迭代次数更少，平均解码吞吐量提高高达 83.3%。在 FPGA 上，与 OMS 解码器相比，SP-MS 解码器可将资源利用率降低高达 56%。