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Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey
Future Generation Computer Systems ( IF 6.2 ) Pub Date : 2021-10-08 , DOI: 10.1016/j.future.2021.09.037
Muhammad Irfan 1, 2 , Abdurrashid Ibrahim Sanka 1 , Zahid Ullah 3 , Ray C.C. Cheung 1
Affiliation  

Content-addressable memory (CAM) is a massively parallel searching device that returns the address of a given search input in one clock cycle. Field-programmable gate array (FPGA)-based CAMs are becoming popular due to their applications in the latest networking systems, e.g., software-defined networks (SDNs) leading to upcoming 5G networks. Ternary CAM (TCAM) implements a routing table in a network router to classify and forward data packets where don’t care bits (X-bits) correspond to multiple addresses. FPGAs do not have a hard-core CAM, although it is a prime element in networking applications. This paper serves as a comprehensive survey on FPGA-based CAM/TCAMs implemented using block random-access memory (BRAM), lookup table RAM (LUTRAM), and flip-flops (FFs). BRAM-based TCAM suffers from the pre-processing of mapping data, requires the data to be in a specific order in some cases, and has a large SRAM/TCAM bit ratio. LUTRAM-based CAM/TCAM suffers from wide bit-wise ANDing, high routing complexity, but has a small SRAM/TCAM bit ratio of 14 compared to 16 in the case of BRAM-based TCAM. Shallow and wide RAM blocks are required to implement large-size RAM-based TCAMs (BRAM-based and LUTRAM-based TCAMs). FF-based TCAMs use FFs as their memory elements and have reduced hardware costs per TCAM bit. However, due to the routing complexity, it suffers from scalability and a large amount of power consumption. The update latency of BRAM-based TCAM and LUTRAM-based TCAM is proportional to the depth of BRAM and LUTRAM, respectively. However, FF-based CAM updates in 1 or 2 clock cycles depending on the availability of input/output pins on target FPGA.



中文翻译:

FPGA 上的可重构内容寻址存储器 (CAM):教程和调查

内容可寻址存储器 (CAM) 是一种大规模并行搜索设备,可在一个时钟周期内返回给定搜索输入的地址。基于现场可编程门阵列 (FPGA) 的 CAM 因其在最新网络系统中的应用而变得越来越流行,例如引领即将到来的 5G 网络的软件定义网络 (SDN)。三元 CAM (TCAM) 在网络路由器中实现路由表,以分类和转发无关位(X 位)对应多个地址的数据包。FPGA 没有硬核 CAM,尽管它是网络应用中的主要元素。本文对使用块随机存取存储器 (BRAM)、查找表 RAM (LUTRAM) 和触发器 (FF) 实现的基于 FPGA 的 CAM/TCAM 进行了全面调查。基于 BRAM 的 TCAM 受制于映射数据的预处理,在某些情况下要求数据按特定顺序排列,并且具有较大的 SRAM/TCAM 位比。基于 LUTRAM 的 CAM/TCAM 受制于宽按位与运算、高路由复杂性,但与基于 BRAM 的 TCAM 情况下的 16 相比,SRAM/TCAM 位比较小,为 14。实现大尺寸基于 RAM 的 TCAM(基于 BRAM 和 LUTRAM 的 TCAM)需要浅和宽 RAM 块。基于 FF 的 TCAM 使用 FF 作为其存储元件,并降低了每个 TCAM 位的硬件成本。然而,由于路由的复杂性,它受到可扩展性和大量功耗的影响。基于 BRAM 的 TCAM 和基于 LUTRAM 的 TCAM 的更新延迟分别与 BRAM 和 LUTRAM 的深度成正比。但是,基于 FF 的 CAM 会在 1 或 2 个时钟周期内更新,具体取决于目标 FPGA 上输入/输出引脚的可用性。

更新日期:2021-11-12
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