It is a real challenge to test asynchronous circuits since there is no clock signal, and there are many non-scan state-holding elements. In this paper, we first propose an Asynchronous Circuit Scan (A-SCAN) latch, which can flip between Valid and Empty states so that we can shift in and out without any clock. Experimental results show that our DFT area and power overhead are 28% and 104% smaller than previous synchronous DFT, respectively. The timing overhead of DFT is nearly two times smaller than previous asynchronous DFT. Based on A-SCAN, we propose the Asynchronous Built-in Self Test (A-BIST), which has no clock. Experimental results show that our BIST area and power overhead are 30% and 116% smaller than previous synchronous counterpart, respectively. Our test coverage is similar to that of ATPG. With A-SCAN and A-BIST, we can easily integrate synchronous and asynchronous testing on the same chip.

由于没有时钟信号，并且有许多非扫描状态保持元件，因此测试异步电路是一个真正的挑战。在本文中，我们首先提出了一种异步电路扫描 (A-SCAN) 锁存器，它可以在 Valid 和 Empty 状态之间切换，以便我们可以在没有任何时钟的情况下移入和移出。实验结果表明，我们的 DFT 面积和功率开销分别比以前的同步 DFT 小 28% 和 104%。DFT 的时序开销比之前的异步 DFT 小近两倍。基于A-SCAN，我们提出了异步内置自检（A-BIST），它没有时钟。实验结果表明，我们的 BIST 面积和功率开销分别比之前的同步对应物小 30% 和 116%。我们的测试覆盖率类似于ATPG。通过 A-SCAN 和 A-BIST，