GaN metal–oxide–semiconductor structures were fabricated by atomic layer deposition of aluminum oxynitride thin films on bulk GaN substrates with c-, a-, and m-plane surfaces. Capacitance–voltage measurements ranging from 5 kHz to 1 MHz were conducted at room temperature. The interface trap number density (N_it) and interface trap level density (D_it) of the devices were extracted. A N_it of less than 2 × 10¹¹ cm⁻² and a D_it of less than 2 × 10¹¹ cm⁻² eV⁻¹ were obtained on the a-plane and m-plane samples. N_it and D_it values were larger for c-plane samples, with the largest interface trap density observed on the c-plane sample with the highest dislocation density. The different N_it and D_it values can be attributed to different dislocation densities and dangling bond densities among different samples.

中文翻译：

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AlOxNy/GaN MOS结构的界面陷阱密度研究

GaN 金属氧化物半导体结构是通过在具有c-、a-和m-平面表面的体 GaN 衬底上原子层沉积氧氮化铝薄膜来制造的。5 kHz 至 1 MHz 范围内的电容-电压测量是在室温下进行的。提取了器件的界面陷阱数密度（N _it）和界面陷阱能级密度（D _it）。甲Ñ_它小于2×10 ¹¹ 厘米^-2和d_它小于2×10 ¹¹ 厘米^-2  eV的^-1分别对所得到的a-平面和m-平面样本。c面样品的N _it和D _it值较大，在具有最高位错密度的c面样品上观察到的界面陷阱密度最大。不同的N _it和D _it值可归因于不同样品之间不同的位错密度和悬键密度。