InP channel planar and vertical MOSFETs utilizing atomic layer deposition of a TiN/Ru gate are fabricated. The performance of the TiN/Ru gate is compared to a Ru-only gate based on the C–V characteristics of MOS (metal–oxide–semiconductor) capacitors and peak transconductance ($g_m$) and subthreshold swing ($\mathrm{SS}$) in planar MOSFETs. Compared to devices with the conventional Ni/Au gate metal, these have a 70 mV/dec $\mathrm{SS}$ [Tseng et al., in Device Research Conference (IEEE, 2019), pp. 183–184.] and a long gate length; TiN/Ru gate devices exhibit an average 68 mV/dec $\mathrm{SS}$, a record low value of InP, suggesting a high quality, low-damage high-k/InP interface. A record high peak $g_m$ of 0.75 mS/μm at $V_{DS}$ = 0.6 V on an InP channel is achieved in a planar gate length ($L_g)=$ 80 nm device. A vertical MOSFET shows a reasonably conformal Ru coverage of the vertical fin and a high 0.42 mS/μm peak $g_m$ for a $L_g$ = 50 nm device. The results of planar and vertical MOSFETs show that TiN/Ru gate metallization via atomic layer deposition is promising for non-planar III–V MOS devices.

中文翻译：

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InP MOSFET 中 TiN/Ru 栅极的原子层沉积

利用 TiN/Ru 栅极的原子层沉积制造 InP 沟道平面和垂直 MOSFET。TiN/Ru 栅极的性能与基于 MOS（金属-氧化物-半导体）电容器的 C-V 特性和峰值跨导（$G_{米}$) 和亚阈值摆幅 ($\mathrm{SS}$) 在平面 MOSFET 中。与具有传统 Ni/Au 栅极金属的器件相比，这些器件具有 70 mV/dec$\mathrm{SS}$[曾等人。, 在器件研究会议(IEEE, 2019), pp. 183–184.] 和长栅极长度；TiN/Ru 栅极器件表现出平均 68 mV/dec$\mathrm{SS}$，创纪录的低 InP 值，表明高质量、低损坏的高 k/InP 界面。创历史新高$G_{米}$0.75毫秒/ μ m，在${伏}_{D秒}$ 在平面栅极长度 (${升}_G)=$80 纳米器件。的纵型MOSFET示出了垂直鳍的一个合理的保形覆盖的Ru和高0.42毫秒/ μ米峰$G_{米}$ 为一个 ${升}_G$= 50 纳米器件。平面和垂直 MOSFET 的结果表明，通过原子层沉积的 TiN/Ru 栅极金属化对于非平面 III-V MOS 器件很有前景。