FinFET architecture has witnessed great success at commercial 22-nm node and beyond due to its natural immunity of short-channel effects (SCEs) since the past decade. As the critical size scales down further, the parasitic capacitance becomes a crucial bottleneck to gain the device performance. In this article, analytical parasitic capacitance models (including eight components) are established based on real Si-bulk FinFET pMOS. Compared with the prior works, first, the electric field distribution with a small gate voltage perturbation is employed to reveal the capacitance origin and distribution. Second, except for widely studied parameters (spacer thickness and overlap), the key parameters [source and drain (S/D) recess depth, spacer height, and embedded-SiGe (e-SiGe) cavity overfill] are also studied. The later parameters are seldom considered, but they are widely selected as key in-line monitor items in manufacturing due to their sensitivity to device current and parasitic capacitance. In addition, the geometric dependence on parasitic capacitance is performed and verified well by the 3-D Sentaurus Technology Computer Aided Design (TCAD) simulator. The result shows that the analytical capacitance model can capture geometric behavior well, which finally is understood by the breakdown of the total parasitic capacitance.

中文翻译：

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基于 Si-Bulk FinFET 的 pMOS 的寄生电容建模

自过去十年以来，FinFET 架构由于其对短沟道效应 (SCE) 的天然免疫力，在商业 22 纳米节点及其他节点上取得了巨大成功。随着临界尺寸进一步缩小，寄生电容成为获得器件性能的关键瓶颈。在本文中，基于真实的 Si-bulk FinFET pMOS 建立了分析寄生电容模型（包括八个组件）。与先前的工作相比，首先，采用具有小栅极电压扰动的电场分布来揭示电容起源和分布。其次，除了广泛研究的参数（间隔层厚度和重叠）之外，还研究了关键参数[源漏（S/D）凹槽深度、间隔层高度和嵌入式SiGe（e-SiGe）腔过填充]。后面的参数很少考虑，但由于它们对器件电流和寄生电容的敏感性，它们被广泛选为制造中的关键在线监控项目。此外，3-D Sentaurus Technology 计算机辅助设计 (TCAD) 模拟器可以很好地执行和验证对寄生电容的几何依赖性。结果表明，解析电容模型可以很好地捕捉几何行为，最终通过总寄生电容的击穿来理解。