A 6T-SRAM bitcell with the footprint of only two transistors is demonstrated by stacking four n-type vertical gate-all-around transistors (VFET) on two pFinFETs. The local interconnects are all within the footprint of the two bottom pFinFETs. The bitcell area is 0.014 μm20.014~\mu \text{m}^{{2}} considering the experimentally achievable metal pitch of 52 nm and bottom pFinFETs of 5 nm node. It can be further reduced to 0.009 μm20.009~\mu \text{m}^{{2}} considering the metal pitch of 30 nm. The minimum operating voltage is analyzed considering the dominant work function variation. The fin height of pFETs and the gate length of nFETs are used to optimize the read/write static noise margin (RSNM/WSNM) for the same bitcell area. The cell ratio is insensitive to pFET fin height and nFET gate length, leading the read stability to be less affected by pFET fin height and nFET gate length as compared to the write stability. The minimum operating voltage is reduced to 0.59 V using pFET fin height of 15 nm and nFET gate length of 20 nm to balance the read/write SNM without assist circuit techniques. The minimum operating voltage can be further improved to 0.56 V by optimizing the threshold voltage of −0.27 and 0.27 V for pFETs and nFETs, respectively. Moreover, using the negative bitline (NBL) technique can provide an additional 320 mV reduction on the write minimum operating voltage.

中文翻译：

---

2T（封装）SRAM 的架构和优化


通过在两个 pFinFET 上堆叠四个 n 型垂直环栅晶体管 (VFET) 来演示仅占用两个晶体管的 6T-SRAM 位单元。局部互连均位于两个底部 pFinFET 的覆盖范围内。考虑到实验上可实现的 52 nm 金属间距和 5 nm 节点的底部 pFinFET，位单元面积为 0.014 μm20.014~\mu \text{m}^{{2}}。考虑到30 nm的金属节距，可以进一步减小到0.009 μm20.009~\mu \text{m}^{{2}}。考虑主要功函数变化来分析最小工作电压。 pFET 的鳍高度和 nFET 的栅极长度用于优化相同位单元区域的读/写静态噪声容限 (RSNM/WSNM)。单元比率对 pFET 鳍片高度和 nFET 栅极长度不敏感，因此与写入稳定性相比，读取稳定性受 pFET 鳍片高度和 nFET 栅极长度的影响较小。使用 15 nm 的 pFET 鳍片高度和 20 nm 的 nFET 栅极长度将最小工作电压降至 0.59 V，以平衡读/写 SNM，无需辅助电路技术。通过分别优化 pFET 和 nFET 的阈值电压 -0.27 V 和 0.27 V，最小工作电压可进一步提高至 0.56 V。此外，使用负位线 (NBL) 技术可以将写入最小工作电压额外降低 320 mV。