This study presents a CMOS image sensor (CIS) with a two-step single-slope (TS-SS) analog-to-digital convertor (ADC), wherein the differential topology characteristics of a ramp generator are used. The proposed TS-SS ADC effectively resolves 1 most significant bit (MSB) with a half-ramping of a full analog-to-digital (A/D) reference at coarse conversion and the remaining least significant bits (LSBs) with differential slope ramping signals from the ramp generator. The proposed readout scheme maintains the existing column readout structure and does not require to regenerate the coarse-step region in each column. Moreover, the proposed TS-SS readout scheme is verified for a frame rate enhancement, that is, the efficiency increases as the bit depth of the ADC increases. A prototype CIS with the proposed 10-bit TS-SS ADC was implemented in a 1P4M 0.11- μm\mu \text{m} CIS process with a 2.9- μm\mu \text{m} pitch. The measurement results of the prototype CIS demonstrated the figure of merits (FoMs) of 102 μV⋅102~\mu \text{V}\cdot pJ/steps and 2.79 μV2.79~\mu \text{V} /MHz/steps.

中文翻译：

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具有使用差分斜坡发生器的两步单斜率 ADC 的 CMOS 图像传感器


本研究提出了一种带有两步单斜率 (TS-SS) 模数转换器 (ADC) 的 CMOS 图像传感器 (CIS)，其中使用了斜坡发生器的差分拓扑特性。所提出的 TS-SS ADC 在粗略转换时通过完整模数 (A/D) 参考的半斜坡有效解析 1 个最高有效位 (MSB)，并通过差分斜率斜坡解析剩余的最低有效位 (LSB)来自斜坡发生器的信号。所提出的读出方案保持了现有的列读出结构，并且不需要在每列中重新生成粗步区域。此外，所提出的 TS-SS 读出方案经过验证可提高帧速率，即效率随着 ADC 位深度的增加而增加。采用所提出的 10 位 TS-SS ADC 的原型 CIS 在 1P4M 0.11-μm\mu\text{m} CIS 工艺中实现，间距为 2.9-μm\mu\text{m}。原型 CIS 的测量结果表明品质因数 (FoMs) 为 102 μV⋅102~\mu \text{V}\cdot pJ/steps 和 2.79 μV2.79~\mu \text{V} /MHz/steps 。