With a goal of delay and power reduction in global buses, an air-gap technology for upper-layer interconnect is introduced. The fabrication process is discussed, utilizing h{h} -BN as an air-gap capping layer to enable large voids. The suitability of an air-gap technology for integration into the upper-layer back-end-of-line (BEOL) interconnect is evaluated in terms of the void ratio to the adjacent-line spacing. Electrical measurements show that adjacent-line capacitance is reduced by 50%. Mechanical reliability is ensured by Young’s modulus above BEOL requirement. Moisture uptake into air gaps is prevented using a hydrophobic capping layer. The integration of air gaps in global buses results in a 41% and 60% reduction in delay and crosstalk in the worst case switching scenario, based on parameters in the 14-nm technology node. It allows a 72% reduction in the energy-delay product with optimally designed repeaters. For the same delay, power consumption in an air-gapped global bus is reduced by requiring 4×4\times fewer repeaters.

中文翻译：

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具有大空隙率的气隙技术可减少全局互连延迟


为了降低全局总线的延迟和功耗，引入了用于上层互连的气隙技术。讨论了利用 h{h} -BN 作为气隙覆盖层以实现大空隙的制造工艺。气隙技术是否适合集成到上层后道工序 (BEOL) 互连中，是根据相邻线间距的空隙比来评估的。电气测量表明，邻线电容减少了 50%。高于 BEOL 要求的杨氏模量确保了机械可靠性。使用疏水覆盖层可防止水分吸收到气隙中。根据 14 纳米技术节点的参数，在最坏的切换场景中，全局总线中气隙的集成可将延迟和串扰减少 41% 和 60%。通过优化设计的中继器，可以将能量延迟乘积减少 72%。对于相同的延迟，气隙全局总线中的功耗由于需要减少 4×4\ 倍的中继器而降低。