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A Full-Featured FPGA-Based Pipelined Architecture for SIFT Extraction
IEEE Access ( IF 3.9 ) Pub Date : 2021-08-12 , DOI: 10.1109/access.2021.3104387
Philipp Kreowsky 1 , Benno Stabernack 1
Affiliation  

Image feature detection is a key task in computer vision. Scale Invariant Feature Transform (SIFT) is a prevalent and well known algorithm for robust feature detection. However, it is computationally demanding and software implementations are not applicable for real-time performance. In this paper, a versatile and pipelined hardware implementation is proposed, that is capable of computing keypoints and rotation invariant descriptors on-chip. All computations are performed in single precision floating-point format which makes it possible to implement the original algorithm with little alteration. Various rotation resolutions and filter kernel sizes are supported for images of any resolution up to ultra-high definition. For full high definition images, 84 fps can be processed. Ultra high definition images can be processed at 21 fps.

中文翻译:

用于 SIFT 提取的全功能基于 FPGA 的流水线架构

图像特征检测是计算机视觉中的一项关键任务。尺度不变特征变换 (SIFT) 是一种流行且众所周知的用于稳健特征检测的算法。但是,它在计算上要求很高,并且软件实现不适用于实时性能。在本文中,提出了一种通用的流水线硬件实现,能够在芯片上计算关键点和旋转不变描述符。所有计算都以单精度浮点格式执行,这使得可以在几乎没有改动的情况下实现原始算法。支持各种旋转分辨率和过滤器内核大小,适用于任何分辨率至超高清的图像。对于全高清图像,可以处理 84 fps。超高清图像可以 21 fps 处理。
更新日期:2021-09-24
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