Recently, several approaches with the ability to reject the DC-offset in phase locked loop (PLL) methods have been developed. These approaches include different filtering structures which can be classified into two categories: prefiltering before the PLL input and in-loop filtering in the PLL control loop. As highlighted in the literature, the DC-offset rejection methods based on in-loop filtering have received less attention due to their slow dynamic performance. Therefore, this paper proposes an alternative DC-offset rejection technique as in-loop filtering of the PLL. The effectiveness of the proposed PLL is confirmed by simulation and experimental results.

中文翻译：

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消除直流偏移以提取电网电压相位和频率的有效方法

最近，已经开发了几种能够抑制锁相环 (PLL) 方法中的 DC 偏移的方法。这些方法包括不同的滤波结构，可分为两类：PLL 输入前的预滤波和 PLL 控制环路中的环路滤波。正如文献中强调的那样，基于环路滤波的 DC 偏移抑制方法由于其缓慢的动态性能而很少受到关注。因此，本文提出了一种替代 DC 偏移抑制技术作为 PLL 的环路滤波。仿真和实验结果证实了所提出的锁相环的有效性。