This paper presents an implementation of a reconfigurable digital down converter (DDC) that can translate high sample rate to lower sample rate signal on field-programmable gate array (FPGA) platform using polyphase filtering. The proposed DDC consists of a polyphase mixer, a cascaded integrator comb (CIC) filter, and a finite impulse response (FIR) filter. The polyphase mixer reduces computational complexity and multiplier blocks simultaneously. Furthermore, the modified CIC filter improves the operating speed, and the new design method of the FIR filter saves memory storage to a great extent. The proposed structure is highly flexible so that the decimation factor can be programmed dynamically during runtime in terms of the sample rate, bandwidth, center frequency, and so on. Moreover, the optimum hardware description language (HDL) coding techniques significantly improve the area efficiency and speed performance of the DDC without compromising the functionality. The proposed design is synthesized using Xilinx Vivado 2020.2 and tested on a Xilinx Kintex-7 FPGA XC7K70T-FBG676 as the target device. Comparison results indicate that the proposed design substantially reduces the resources as well as power. A verification test is to certify the feasibility and correctness of the hardware implementation. The proposed DDC is well-matched in any digital radio application.

本文介绍了一种可重构数字下变频器 (DDC) 的实现，它可以使用多相滤波在现场可编程门阵列 (FPGA) 平台上将高采样率转换为较低的采样率信号。建议的 DDC 由多相混频器、级联积分梳状 (CIC) 滤波器和有限脉冲响应 (FIR) 滤波器组成。多相混频器同时降低了计算复杂度和乘法器块。此外，改进的CIC滤波器提高了运算速度，FIR滤波器的新设计方法在很大程度上节省了内存。所提出的结构非常灵活，因此可以在运行时根据采样率、带宽、中心频率等动态地对抽取因子进行编程。而且，最佳硬件描述语言 (HDL) 编码技术在不影响功能的情况下显着提高了 DDC 的面积效率和速度性能。建议的设计使用 Xilinx Vivado 2020.2 进行综合，并在 Xilinx Kintex-7 FPGA XC7K70T-FBG676 作为目标器件上进行测试。比较结果表明，所提出的设计大大减少了资源和功耗。验证测试是为了证明硬件实现的可行性和正确性。建议的 DDC 在任何数字无线电应用中都能很好地匹配。比较结果表明，所提出的设计大大减少了资源和功耗。验证测试是为了证明硬件实现的可行性和正确性。建议的 DDC 在任何数字无线电应用中都能很好地匹配。比较结果表明，所提出的设计大大减少了资源和功耗。验证测试是为了证明硬件实现的可行性和正确性。建议的 DDC 在任何数字无线电应用中都能很好地匹配。